The invention relates to a circuit configuration for converting logic levels.
Modern CMOS technologies already make possible operating frequencies of several hundred MHz. However, in the past it has not been practicable to utilize pure CMOS circuit technology in frequency ranges wherein mobile radiotelephone applications are operated. These are frequencies in the range of 900 MHz, 1800 MHz, and 1900 MHz, for example.
In digital CMOS circuit technology, it is common for the logic states high and low to correspond to the upper and lower supply voltages, respectively (rail to rail logic). Consequently, it is necessary to cross over the complete range of supply voltages each time the logic state is switched from high to low or vice versa. This means that parasitic capacitors must be recharged to maximum with each switching process. For this reason, the dynamic power consumption of a CMOS logic is very high. Another disadvantage of this CMOS logic is that high noise levels are generated on the supply potential and the reference potential by the switching processes. The currently achievable rail-to-rail switching speeds are not yet high enough to be utilized in frequency ranges of several GHz, and consequently this circuit technology cannot yet be reasonably utilized in applications in mobile radiotelephone frequency ranges.
A differential logic with slight differences between the logic levels high and low, which has a similar structure to an SML or BCL logic such as is known from bipolar switching technology, is therefore standard in the current state of the art for the highest switching speeds in the GHz range.
In processing lower frequencies, rail to rail CMOS circuitry has a low space consumption, no static power consumption, and high resistance to noise, and saves bias currents as well. For these reasons, modern circuit designs utilize BICMOS processes, wherein complete bipolar and CMOS processes are unified. The circuit parts that operate at high frequencies are built in bipolar technology (CML/ECL), and the lower frequencies are processed using rail to rail CMPS logics.
The problem arises that an interface must be formed between the two circuit parts with ECL/CML logic levels and CMOS logic levels. The ECL/CML logic levels are present in differential form; they typically comprise a voltage range of approx. xc2x1100 mV on each of the two signal lines; and they are situated symmetrically relative to a mid-potential. By contrast, the CMOS circuit parts are furnished with a separate voltage supply and comprise logic levels ranging from the CMOS supply potential to the (common) ground potential.
CMOS gates have a steep switchover characteristic in a limited switchover voltage range wherein the gates switch rapidly. The switchover point of a CMOS gate is dependent upon both the temperature and the supply voltage, as well as on process fluctuations in the production process. A direct coupling of bipolar and CMOS circuits is difficult in practice, since the production tolerances in the bipolar and CMOS circuit parts correlate with each other poorly if at all, so that they disadvantageously leak, and the correct switching behavior is no longer guaranteed owing to divergent bias conditions.
One solution to this problem, which is disclosed in U.S. Pat. No. 6,008,667, is to use the two levels of a differential logic signal as an input signal and to convert the logic level accordingly.
The object of the present invention is to provide a circuit configuration for converting logic levels which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which makes possible a larger limit frequency given a smaller noise factor.
With the above and other objects in view there is provided, in accordance with the invention, a circuit configuration for converting logic levels, comprising:
a first bipolar transistor having an emitter, a collector, and a base;
a second bipolar transistor having an emitter, a collector, and a base;
a first current source connected to the emitter of the first bipolar transistor and to the emitter of the second bipolar transistor;
a second current source connected to the collector of the first bipolar transistor;
a third current source connected to the collector of the second bipolar transistor;
an input-output feedback inverter connected to the collector of the first bipolar transistor; and
an output node connected to and controllable by the input-output feedback inverter.
In other words, the objects are achieved by a circuit configuration for converting logic levels which includes a first bipolar transistor comprising an emitter, a collector and a base and a second bipolar transistor comprising an emitter, a collector and a base; whereby the emitter of the first bipolar transistor and the emitter of the second bipolar transistor are connected to a first current source; the collector of the first bipolar transistor is connected to a second current source; and the collector of the second bipolar transistor is connected to a third current source; and whereby a first input-output feedback inverter is connected to the collector of the first bipolar transistor, and an output node is activatable by the first feedback transistor.
In the operation of the circuit, a differential logic signal is applied to the base of the first bipolar transistor and to the base of the second bipolar transistor as the input signal. If there is no difference between the voltages at the bases of the first and second transistors, the sum of the two currents impressed on the collectors equals the current which flows through the common emitter current source. In this case, the first inverter is in an idle state. However, if there is a difference in the voltages of the first and second bases, a greater current flows through one of the bipolar transistors, and a smaller current flows through the other bipolar transistor. In this case, the additional current is delivered from the output of the first inverter. In this context, the term xe2x80x9cinput-output feedback inverterxe2x80x9d refers to an inverter whose input and output are connected to each other.
Since the output voltage of the first inverter thus varies, this can be compared to a reference at the output node in order to deliver an output signal with CMOS logic levels. The feedback inverter acts here as a current-voltage converter whose characteristic puts it in the position to hold a node at a voltage value given low impedance. The advantage of this is that a greater limit frequency is achieved, since the inverter comprises a high driver power.
In accordance with an added feature of the invention, in addition to the first above-noted input-output feedback inverter a second input-output feedback inverter is connected to the collector of the second bipolar transistor, and the output node is connected to and controlled with the aid of the second feedback inverter. The output voltage of the first feedback inverter can be compared to the output voltage of the second feedback inverter in the output node. Since the two bipolar transistors work in opposite directions, the signals generated by the two feedback inverters also run in opposite directions, which expediently expands the signal range.
In accordance with an additional feature of the invention, the first inverter and the second inverter are coupled via a current mirror. This development is particularly advantageous due to the ability to convert the voltages at the feedback inverters with the aid of transistors into currents, which can then be compared to each other in the output node with the aid of the current mirror.
In accordance with another feature of the invention, the circuit further comprises:
a first transistor having a drain, a second transistor having a drain, and a first node connected between the drain, the first transistor having a gate connected to the collector of the first bipolar transistor, and the second transistor having a gate connected to the first node; and
a third transistor having a drain connected to the output node and a fourth transistor having a drain connected to the output node, the third transistor having a gate connected to the gate of the second transistor, and the fourth transistor having a gate connected to the second feedback inverter.
The advantage of said circuit configuration is that the output voltages of the first and second inverters can be compared in the output node to the current through the fourth transistor with the aid of a first transistor and the current reflecting device which comprises the second and third transistors.
In accordance with a further feature of the invention, an operational amplifier has a first input connected to a third input-output feedback inverter, a second input, and an output connected to a control input of the second and third current sources. That is, an operational amplifier with first and second inputs and an output be so arranged that the first input is connected to a third input-output feedback inverter, whereas the output is connected to a control input of the second current source and to a control input of the third current source. The advantage of the operational amplifier is that the operating point of the first and second inverters is set with the aid of a third feedback inverter.
In accordance with a concomitant feature of the invention, a third inverter has an input connected to the collector of the first bipolar transistor, and an output connected to the collector of the second bipolar transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for converting logic levels, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.